This application claims priority to Korean Patent Application No. 2004-0020764, filed on Mar. 26, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to memory module systems, and more particularly to a memory module system having an activated memory device controlling on-die termination of at least one inactivated memory device for efficient control.
2. Description of the Related Art
Semiconductor devices include receiving circuits for receiving signals via input pads and include output circuits for outputting signals via output pads. Due to high operating speed, the swing width of signals exchanged between semiconductor devices is decreased to minimize delay time of signal transmission.
However with such decreased swing width, influence of external noise increases such that signal reflection from impedance mismatch at an interface point becomes more critical. Such an impedance mismatch degrades high-speed data transmission as output data from an output node of a semiconductor device is distorted. Another semiconductor device receives the distorted output signal with possible setup/hold fail or misjudgment of input level.
Therefore, the semiconductor device at the receiving end includes an impedance matching circuit commonly referred to as “on-die termination” or “on-chip termination” coupled to an input pad. In a general on-die termination scheme, source termination is performed by the output circuit of a first semiconductor device at the transmitting end. Additionally, parallel termination is performed by the receiving circuit of a second semiconductor device at the receiving end.
A point-to-point connection structure is the simplest channel connect structure and is amenable for high-speed data transmission. The point-to-point connection structure typically uses on-die termination (ODT) to improve signal fidelity of channels. Although the point-to-point connection structure provides optimum signal fidelity, a signal line is allocated to each connection such that the point-to-point connection structure may not be amenable for high-bandwidth data transmission.
A memory system requires high bandwidth for high capacity data transmission in addition to high-speed data transmission. Therefore, a memory system implements “ranks” to meet both the requirements. With such ranks, the memory system includes point-to-multipoint connections between a controller and memory devices. However, using a rank selection signal, a point-to-point connection is established for signal transmission between the controller and the memory devices. In such a memory system, ODT is commonly used to improve signal fidelity of channels with each memory device of the memory system including respective ODT therein.
FIG. 1 is a block diagram of a conventional dual rank memory system. Referring to FIG. 1, the dual rank memory system includes first and second memory devices DRAMA and DRAMB each coupled to one signal connection point. A respective ODT circuit is formed within each of the memory devices DRAMA and DRAMB. A first ODT circuit RodtDramA is formed within the first memory device DRAMA, and a second ODT circuit RodtDramB is formed within the second memory device DRAMB.
Table 1 illustrates different methods of controlling activation of the ODT circuits, RodtDramA and RodtDramB, when the first memory device DRAMA is activated for a data read or write.
TABLE 1ODT Control MethodRodtDramARodtDramBSelf-OnOnOffBoth-OnOnOnOther-OnOffOn
Hereinafter, the activated memory device is the memory device that is selected for data read or write. Any other memory device(s) that is not selected for data read or write is referred to as an inactivated memory device.
In a self-on control method, the respective ODT circuit of the activated memory device is turned “on” while the respective ODT circuit of the inactivated memory device is turned “off.” When the first memory device DRAMA is activated, the first ODT circuit RodtDramA is activated while the second ODT circuit RodtDramB of the inactivated second memory device DRAMB is inactivated.
Generally, when an ODT circuit is referred to as being activated (i.e., turned on), the ODT circuit provides a finite resistance at an I/O (input/output) pad of the semiconductor device. When the ODT circuit is referred to as being inactivated (i.e., turned off), the ODT circuit is open-circuited for not affecting the resistance at the I/O (input/output) pad of the semiconductor device.
Further referring to Table 1, in a both-on control method, the ODT circuits of both the activated and inactivated memory devices are turned “on”. In the example of the first memory device DRAMA being activated, both the first and second ODT circuits RodtDramA and RodtDramB are activated.
In an other-on control method, the respective ODT circuit of the activated memory device is turned “off”, and the respective ODT circuit of the inactivated memory device is turned “on”. In the example of the first memory device DRAMA being activated, the first ODT circuit RodtDramA is inactivated while the second ODT circuit RodtDramB of the inactivated second memory device DRAMB is activated.
FIG. 2 illustrates channel characteristic simulation results for such three types of control methods in the dual rank memory system of FIG. 1. Referring to FIG. 2, (a), (b), and (c) illustrate channel characteristic results according to the self-on control method, the both-on control method, and the other-on control method, respectively.
For impedance matching to a channel, Rodt (ODT resistance) is set to be substantially equal to ZO (impedance of a channel) if one DRAM ODT is coupled to the channel. Alternatively, for impedance matching to the channel with two DRAM ODTs being coupled to the channel, Rodt within each DRAM is set to be substantially equal to 2×ZO. However in reality as shown in the simulation result of FIG. 2, best signal fidelity is achieved for the other-on control method due to effects of various parasitic elements in the channel.
Such variance of signal fidelity among the ODT control methods is not significant in conventional memory systems. However, as overall timing budget is decreasing for higher-speed memory systems, variance of signal fidelity among the ODT control methods becomes important. In addition, lower power consumption is becoming important for modern portable applications. Thus, efficient ODT control with high signal fidelity and low power consumption is desired.